Circuit designs for integrated circuits (ICs) can be generated using a variety of techniques. In some examples, designers can write register-transfer level (RTL) code, write program-language code, create schematic representations, or a combination thereof to design a circuit for implementation in a target IC device. The target IC device can be a programmable IC, such as a field programmable gate array (FPGA), a mask-programmable IC, such as an application specific integrated circuit (ASIC), or the like. In the design flow, a designer creates a description of the circuit design, which is then processed through one or more steps that transform the description into a physical implementation of the circuit design for a target IC device.
In modern IC design, designing a circuit to meet timing performance goals (i.e., operating frequency goals) is one of the most challenging issues faced by designers. Circuit designers spend significant time and energy to have their designs meeting timing goals. Often times, place, route, and physical optimization tools are not effective at identifying the bottleneck paths in the circuit design that can be optimized to improve timing performance. Moreover, when processing a placed and routed circuit design for an IC, traditional physical optimization tools can suffer from long run times, making them impractical to use.